Positron designs chips that do one thing: run large-model inference. The bet is that inference is bound by how much memory you have and how fast you read it, not by peak matrix throughput, so the company builds around commodity memory instead of the scarce high-bandwidth memory GPUs fight over. Its shipping product, Atlas, is by the company’s account an FPGA-based inference server that beats comparable Nvidia GPU systems on performance per dollar and per watt; read both the architecture and the comparison as Positron’s claims to probe. Atlas is in production, with a reported 50-plus-rack deployment on Oracle Cloud Infrastructure and named customers including Jump Trading and i3d.net.
The bigger story for anyone interviewing is the next chip. Asimov is Positron’s first custom ASIC, pairing its architecture with commodity LPDDR5X memory the company puts at 288 GB to 2,304 GB per chip, slated to tape out on TSMC’s N3P process at the end of 2026 with production targeted for the second half of 2027. Above it sits Titan, a node of four to eight Asimov parts aimed at models beyond 16 trillion parameters and context past 10 million tokens. The September 2026 Series C, roughly $375 million now plus up to $500 million in a follow-on tranche, set the $5 billion post-money valuation on a $3.5 billion pre-money. It followed a reported $230 million Series B in February 2026 at over $1 billion, a $51.6 million Series A in mid-2025, and a $23.5 million seed. Positron was founded in 2023.
Leadership tells you what the interviews weigh. By their public profiles, CEO Mitesh Agrawal was previously an executive at Lambda, CTO Thomas Sohmers is a former Thiel Fellow who was Groq’s director of technology strategy before co-founding Positron, and Chief Scientist Edward Kmett is known in functional-programming and compiler circles. That bench hires people who can reason about hardware, numerics, and the software that maps a model onto silicon.
What is documented about the process, and what isn’t
Look at the evidence plainly. Positron does not publish an interview process, and it has almost no first-hand candidate write-ups: as of September 2026 we found no interview reports on Glassdoor and no substantive Blind thread, only listings. So this guide separates two things. What is known: the open roles and, on a couple of listings, the posted base-salary range. What is inferable: what a loop for each role most likely probes, from the job descriptions and from how comparable chip and inference companies interview. Any confirmed “Positron loop” you see right now is invented. On a recruiter call, the most useful question is to have them walk you through the exact stages for your requisition, because you cannot look them up.
Why the questions look the way they do
The architecture is the study guide. A memory-first inference chip forces a specific set of conversations, and the interviews pull from it. Why does a long-context model become memory-bound? Because the key-value cache grows with sequence length and batch size, and at a 10-million-token context that cache, not the weights, dominates footprint and bandwidth. Trading scarce HBM for abundant LPDDR5X buys capacity at lower bandwidth per dollar, which reshapes the roofline: you hold enormous state but schedule around slower reads. Expect to reason out loud about batching in a bandwidth-limited regime, where quantization buys headroom without wrecking quality, and the arithmetic intensity of what you are mapping. None of it requires insider knowledge; it comes straight from Asimov’s public description.
The table groups the roles Positron is posting, with what each builds on today and what a loop would most plausibly test. The third column is informed inference.
| Role family at Positron AI | What it works on now | What a loop would most likely probe | Publicly posted base range (Sept 2026) |
|---|---|---|---|
| ASIC architecture and design verification | Asimov microarchitecture, RTL, and the verification environment ahead of an end-of-2026 tape-out | Digital design depth, RTL and SystemVerilog, UVM-style verification, datapath and memory-subsystem tradeoffs | Not posted for these titles; ask the recruiter |
| Physical design and silicon validation | Getting Asimov through N3P implementation and, later, bring-up and validation of first silicon | Place-and-route, timing closure, power and area tradeoffs, post-silicon debug for validation roles | Senior ASIC physical design listed at $150,000-$250,000 |
| Compiler and runtime | The stack that lowers a model to Asimov: graph capture, scheduling, memory planning, kernels | Compiler internals, IR and scheduling, correctness under quantization, reasoning about a memory-bound target | Not posted for these titles; ask the recruiter |
| ML-infrastructure and inference serving | Serving stack above the chip: batching, KV-cache management, model coverage, numerics | Inference-serving systems, throughput and latency tradeoffs, quantization, distributed serving of very large models | Not posted for these titles; ask the recruiter |
| Forward-deployed and technical product planning | Landing Atlas and later Titan at customers; planning silicon, systems, and software roadmaps | Systems breadth end to end, customer-facing framing, translating model needs into hardware specs | Silicon-and-systems product planning listed at $200,000-$350,000 |
If you are on the ASIC hardware track
This is the center of gravity right now; Asimov has to tape out at the end of 2026. Design and verification candidates should expect the depth a pre-tape-out ASIC team screens for: fluent digital design, RTL in SystemVerilog or Verilog, and, for verification roles, real command of a constrained-random, coverage-driven methodology like UVM. Physical-design candidates get the implementation side: place-and-route, static timing, clock and power planning, and the area-versus-timing tradeoffs that decide whether a block closes. Two things are specific to Positron. The memory subsystem is the product, so questions about feeding LPDDR5X, bandwidth, and on-chip buffering carry more weight here than at a compute-first shop. And because Atlas is FPGA-based today while Asimov is an ASIC arriving in 2027, both FPGA/RTL experience and tape-out experience are live; the postings for silicon validation and hardware security signal that bring-up is already staffing up. Confirm which side of that line your req sits on.
If you are on the compiler, runtime, or ML-infra track
Positron’s own product-planning listing names numerics, quantization, linear algebra, runtimes, and inference-serving stacks, which is a good map of what these interviews cover. Compiler candidates should be ready to talk about lowering a model graph to hardware: intermediate representations, scheduling and fusion, memory planning, and keeping numerics correct when you quantize. Make one tradeoff concrete: on a decode step bound by reading weights and KV-cache out of LPDDR5X, do you fuse two kernels to save a memory round-trip or keep them apart for a cleaner tiling, and what does the arithmetic intensity of each say? With Kmett as chief scientist, expect real depth on IR design and correctness, but there is no evidence they interview in a specific language, so prepare the concepts rather than a syntax. ML-infra and serving candidates should drill batching, KV-cache management, and throughput-versus-latency tradeoffs, and work one out loud. At a 10-million-token context the KV-cache, not the weights, is what you stream, so a larger batch amortizes weight reads but multiplies cache traffic against a fixed LPDDR5X budget; the answer they want is where that crossover sits and how quantizing the cache shifts it. A pass through time and space complexity covers the algorithmic baseline, but the differentiator is that systems reasoning, which the muscles from a set of system-design interview guides transfer to as long as you keep the design grounded in inference rather than a generic web service. Because this loop is unpublished, the closest public analogues are the other inference-chip startups: Groq’s compiler-and-inference loop runs a domain-depth round on its LPU architecture and a low-level coding round on memory layout and concurrency, and Cerebras interviews engineers on wafer-scale roofline reasoning, tiling, and weight-streaming. Both map almost directly onto what Positron’s memory-first design would test.
Forward-deployed and product-planning roles
These are the least algorithmic and the most end-to-end. A forward-deployed engineer lands Atlas at the trading and hosting customers already named, so the interview leans on systems breadth and on turning a customer’s model and latency targets into a deployment. The two technical-product-planning roles, for silicon-and-systems and for AI inference and software stacks, span from memory technology and networking up to serving; the conversation is about judgment across that range, not a single coding problem.
How to read the comp
Only two base ranges are public, both in the table above, and each is the listing for one requisition, not “what Positron pays”: bands move with level, location, and role, and most open titles post no number. The larger piece is equity. At a $5 billion post-money valuation the options or RSUs are real but illiquid, and the chip is not in production until the second half of 2027, so the value is a bet on execution, not cash you can touch. Pin down which instrument you are getting, the strike or grant price, the vesting schedule, and the level, since level drives the number more than negotiation does. Run the offer through a total-comp calculator against the current valuation, and a salary-negotiation walkthrough covers how to push base. Whatever a recruiter quotes, the pay-transparency range on the exact posting is your real anchor.
How to prepare
Prepare for your specific track. Hardware candidates should put their hours into RTL, verification methodology, and, for physical-design roles, timing and power, plus a clear story about the memory subsystem that defines this product. Compiler and infra candidates should reason from a model down to a memory-bound chip and back, with quantization and KV-cache management front of mind. A behavioral round is close to certain even though the loop is unpublished, since a startup staffing a tape-out screens for it like any company its size, and a couple of tight ownership stories beat improvised ones; the STAR structure keeps them from wandering. Run your resume through a resume checker so it quantifies the silicon or systems you have shipped, and if you are weighing Positron against the field, the AI-startup interview guides and the difficulty index put it next to its peers. Positron gets grouped with Groq, Cerebras, SambaNova, and Etched because they are all chasing inference silicon, and those last two guides show how similar the loops look across the field, but Positron’s memory-first thesis is the thing your interview will keep coming back to, so make sure you can argue it both ways.
Here the interview is inferable from the architecture and the postings, not from Glassdoor transcripts, because those do not exist yet. That is an advantage if you do the reading. Show up able to reason about why inference is memory-bound and what it costs to trade bandwidth for capacity, and you answer the question Positron cares about before anyone asks it.
